[Hardware Router] Weekly Progress 4/30 - 5/06

Monday - Designed a simple Cyclic Redundancy Check module in verilog in order to modify the frame check sequence of Ethernet frames, as a first step in developing Ethernet for the DE4 board (in hardware). The frame check sequence is a portion of the Ethernet Frame Header that requires a CRC (Cyclic Redundancy Check) in order to determine whether or not the frame was transmitted properly. The CRC Module uses bitwise XOR with specific bits of data, and an enable bit, in order to generate the checksum. A so-called "magic number" of
32'hC704DD7B is used to determine whether or not an error has taken place. The "magic number" is calculated from a polynomial value. If there was an error, then the frame has tainted data, and must be discarded or corrected.

Tuesday - Designed simple FIFO to be used as a packet buffer and a Tristate Controller for use with the data pathways. The FIFO will hold the data from the Ethernet frames, as they come in, and release them after the headers are modified and the destination selected. The tristate controller will be used to output a hi-Z value onto the data line from one end so that the bus can be used by other locations. Went home early today due to sore throat.

Wednesday through Saturday - Home sick with influenza.

Sunday - Began work on initialization module. This module is used to initialize the PHY of the DE4 board. Each PHY should be reset for a period of time (several milliseconds?) in order for it to work properly when turned on. Use a simple counter and case statement to determine when to halt the reset.