[Hardware Router] Development (5/15 - 5/16)

Today I received an email from Professor Tessier at the University of Massachusetts Amherst, who worked on a version of the NetFPGA platform compatible with Altera boards.

Examining the files sent by Professor Tessier, development was begun based on the NetFPGA platform. The NetFPGA was originally designed for use on Xilinx boards, but a modification of the system files should allow it to work on the Altera DE4 board.

Analyzing the system's implementation, it seems that the Ethernet controller is implemented largely in hardware. The port interfaces are instantiated in verilog by means of sequential always blocks causing the ports to advertise a "ready" signal unless synchronous reset signal is sent. Continuous assignments then set the ready signals. The rest of the assignments are also handled with continuous 'assign' statements. The NetFPGA core module is instantiated to provide error detection through the CRC checker. The core module also pipes data into the interfaces.

The NetFPGA Core module acts as the main top level design (with some exceptions). The SRAM and other storage structures (FIFOs) are instantiated here, and the logic in the core provides for the sending and acknowledgment portion of network connectivity. Frame errors are generated here, as well as other Ethernet sink errors, such as those dealing with malformed datagrams. Additionally, data path transmission is taken care of in this module, including timing and control signal handling.

Other portions of the design, such as various FIFOs used to hold Ethernet frame data, including payloads and header/tail fields, are self-explanatory.

Finally, the system relies on configuration scripts sent through the JTAG interface in order to configure the device. That is, instead of having the MAC addresses, IP addresses, routing tables, and ARP data hard-coded into the verilog (which would result in very tedious recompilation complications), user scripts are used to dynamically allocate all of the data during initial setup on runtime. After initial setup, the router is self-sufficient, but the JTAG connection may be maintained to maintain output of data relevant to debugging.

Next step is designing routing services for the device...