[Hardware Router] Layer 3 Perspective

The following is a design specification of the hardware router, from a layer 3 perspective:

• Receive Packet
• Delimit data according to Ethernet Standard
• Store delimited data in 2D Array (memory)
• Analyze Packet
• Extract relevant header information
• Store information in temporary registers for ease of access\
• Decide what to do with packet
• Exception for own IP (must respond if valid packet)
• If unrecognized information, drop packet.
• Also drop if TTL = 0
• Associate outbound port with packet by modifying bits directly in the queue
• Modify Packet Data
• Change destination IP to destination associated with chosen outbound port
• Change source address to IP of outbound port
• Subtract from TTL
• Recalculate checksum and set it
• Checksum is the 16-bit one's complement of the one's complement sum of all 16-bit words in the header.
• Example checksum calculation, for IP Header: 4500003044224000800600008C7C19ACAE241E2B (20 byte header).
•  4500+0030+4422+4000+8006+0000+8C7C+19AC+AE24+1E2B = 2BBCF
• 2 + BBCF = BBD1 = 1011101111010001 -> 1's comp = 0100010000101110
• Checksum = 442E
• Send Packet
• Write to outbound port using Ethernet protocol
• Delete data for sent packet from memory and shift all other members of the array up (FIFO).

This is the top-level design. In order for it to work, we must first implement Ethernet protocol on the board.

Post describing Ethernet implementation will follow.