NIOSII-Week5

This week I worked on SOPC builder and setting the pins for the components.
Components in the SOPC are
CPU
Tristate Bridge
LAN
RAM/ROM
Timer
Timer 2
JTAG
UART
System ID
FLASH
SRAM
SDRAM
PIO

Added all verilog files from SOPC to project. FPGA pins from SOPC builder are all set.
There was problem when compiling with data0 and tri_state_bus_data being in the same pin.
I looked at the qsf file of the standard layout and found how to fix the problem. I had to add
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" to my qsf file to make it work. I was able to compile. When I try to run hello world
I get error where ELF proccess failed. So that means there is something wrong with the pins/mem/design that maked ELF unable to load.

Fixed ELF proccess failed, reason was the there was no clk. Had to create 50mhz clock in timing analyzer. Was able to run Hello World on onchip mem.